1. Field of the Invention
This invention relates to electrically writable and erasable nonvolatile semiconductor memory devices, including electrically erasable programmable read only memory (EEPROM) devices. More particularly but not exclusively, the invention relates to write schemes of nonvolatile semiconductor memory devices utilizing write techniques based on “hot” electron injection.
2. Description of the Related Art
Flash EEPROM devices include flash memories of the so-called NOR type, which are designed to make use of write schemes based on injection of hot electrons. See FIG. 16. This diagram shows typical bias conditions during writing of a memory cell MC in a NOR-flash memory chip. This memory cell MC has a stacked gate transistor structure, including a floating gate 103 and a control gate 105 above a silicon substrate 100. The floating gate 103 is formed above a p-type semiconductor well region 101 in the silicon substrate 100, with a tunneling dielectric film 102 being interposed between the well 101 and floating gate 103. The control gate 105 is formed to overlie this floating gate 103 with an interlayer dielectric film 104 therebetween. This film 104 is called the “inter-gate” insulator film. Source 106 and drain 107 are formed so that these are self-aligned with control gate 105. Control gate 105 is connected to a corresponding one of word lines, while drain 107 is coupled to a corresponding one of bit lines through a column gate. Source 106 is coupled to a common source line.
During data writing, as shown in FIG. 16, apply a write voltage of 10 volts (V) to the control gate 105 and apply the drain 107 with either a voltage of 5V (in the case of logic “0” data) or a low level power source voltage Vss (in the case of logic “1” data) while letting the p-type well 101 and source 106 be set at 0V. With such voltage application, the memory cell MC turns on permitting flow of a large drain current (write current) Iprg at the time of logic “0” data write. This current flow results in production of hot electrons. These hot electrons are injected to the floating gate 103 by the presence of a high electric field between the control gate and the channel, and are then trapped at floating gate 103.
A high threshold voltage state with electrons trapped at the floating gate 103 is regarded as data “0” storage (write state), by way of example. Data erase is performed in a way which follows. Apply an erase voltage, which has its polarity that causes p-well 101 to become positive, between the control gate 105 and p-well 101 to thereby force the electrons of floating gate 103 to draw out toward the channel side in the form of a Fowler-Nordheim (FN) tunneling current. This results in establishment of a low threshold voltage state with the electrons drawn out of floating gate 103, which is regarded as data “1” storage (erase state).
A high level power source voltage to be used during data writing and erasing is produced by potential boosting circuitry employing charge pump architectures. The booster circuitry includes a part that gives the drain voltage during writing. This part is required to offer large current supplying capability for production of hot electrons in the way stated above. Unfortunately, presently available standard charge pump circuits are less in current supplying ability. Accordingly, with prior known write schemes using hot electron injection, a number of data bits (cell number) capable of being written simultaneously is determined by the current supply ability of such booster circuit part for giving the drain voltage. Generally the simultaneous writable data bits are limited in number to four (4) to sixteen (16) bits.
Consequently, one typical approach to achieving the so-called “page program” functionality that automatically performs writing of a page of data bits (for example, 64 bits) is as follows. While loading a page of data bits together from the outside of a chip, within-the-page or “intra-page” access is done inside the chip to thereby permit execution of data write for a column of addresses (e.g. 8 bits) at a time. This per-column write technique will be explained in detail below.
FIG. 17 is a basic flow chart of a procedure of one typical automated write function that is often employed in flash memory chips. The term “automated write” as used herein may refer to a function that performs write and verify operations while a chip per se automatically controls internal voltage potentials and sense amplifiers after receipt of a write command along with a write address and write data. After having received and accepted the write command and write address/data, the procedure goes to step S1 which determines whether the chip is presently in a write inhibition (protect) state. If the answer is NO at step S1, that is, when the chip is not in the protect state, then the procedure goes to step S2 which performs write set-up. Next, proceed to step S3 which executes writing. After completion of writing, go to step S4 for verify setup and then go to step S5 that performs verify-read to thereby determine whether desired data was written successfully.
At the verify-check step S5, detection is done on a per-bit basis to determine whether the data bit to be written and the actually written data are identical to each other. If all the bits involved do not pass the test, i.e. if NO at step S5, then the procedure goes next to step S6 which determines the next write data, followed by repeated execution of write and verify operations. Note here that the language “determine[s] the write data” means an operation which appropriately controls write data transmission so that the write voltage is no longer applied in the next cycle to the drain of a certain memory cell in which a logic “0” data bit has already been written.
FIG. 18 shows potential changes of a word line WL and a bit line BL in such auto-write process flow of FIG. 17. The write and verify-read setup sessions (at steps S2 and S4) are mainly a wait time taken for the write voltage being applied to wordline WL to become stable in potential. In most cases the write and verify-read require consumption of a time which is almost equal in length to a write time period, although the time length is variable depending upon the performance of power supply control circuitry.
In the process flow of FIG. 17, only a write event is shown with respect to any given one address. Recall that the page write or “program” operation is for inputting and latching a series of continuous data bits corresponding to multiple addresses upon inputting of a write command and then automatically performing writing with respect to all of them in a similar way. In the case of this page programming, the flow of a write process is as shown in FIG. 19. This is a scheme for performing a write/verify process loop on a per-address basis.
For the first address, perform write/verify in a similar way to the flow of FIG. 17 and repeat writing until the verify test is passed. When the verify is passed at step S5, the procedure goes to step S7 which determines whether a present address is the final address. If NO at step S7, then proceed to step S8 which increases or “counts up” a present address by one, followed by execution of similar write/verify operations. This write/verify cycle will be repeated with respect to every address within a page until write passes the verify test.
The relevant art page program sequence shown in FIG. 19 is faced with a problem that write setup is required per address, resulting in an unwanted increase in length of a time taken to complete the page programming.
This invention has been made in view of the technical background stated above, and an object of the invention is to provide a nonvolatile semiconductor memory device capable of performing page programming at high speeds.